Building an FPGA RGB-to-HDMI Converter for the Sharp X68000

The Sharp X68000 remains an unusually rewarding computer to preserve because its video output sits between familiar home-computer RGB and the more demanding timing of arcade hardware. A modern LCD may accept one mode perfectly while losing sync on another, even when the picture appears electrically healthy on an older CRT. An FPGA-based RGB-to-HDMI converter gives the platform a dependable digital video path without changing the character of the original hardware.

The project involves more than wiring an RGB connector to an HDMI socket. The analogue signals must be protected and sampled, horizontal and vertical timing must be identified, pixels must be reconstructed, and the resulting image must be scaled into a display mode that ordinary televisions and monitors understand. The design also needs clean power, sensible grounding and an enclosure suitable for a valuable Japanese computer.

For builders in Australia, the practical environment matters. Most X68000 machines arrive through Japanese auctions or specialist imports, replacement cables can take weeks to reach Brisbane or Perth, and local HDMI screens are generally far less tolerant of unusual 15 kHz and 24 kHz timings than period displays. A careful converter can make an imported machine much easier to use while preserving an original RGB connection for future repairs.

Start With The X68000 Signal

Begin by identifying the exact output format of the computer being modified or connected. X68000 models can use several horizontal frequencies, including approximately 15 kHz, 24 kHz and 31 kHz, with separate combinations of resolution and refresh timing. The connector may carry analogue red, green and blue together with synchronisation signals, but the sync arrangement and electrical details should be verified against the model’s service information rather than assumed from a generic VGA pinout.

A practical first instrument is an oscilloscope with a suitably grounded probe. Check the voltage range on each colour channel, the polarity and amplitude of sync, and the time between horizontal edges. A logic analyser can help classify timing, but it should not be connected directly to an unknown analogue signal. If the machine has a faulty power supply, unstable clock or noisy video output, an HDMI converter may simply reproduce the fault in a more confusing form.

The Nereid-X expansion board is a useful reminder that X68000 projects often combine careful hardware engineering with practical modern interfaces. A video converter should follow that same approach: remain electrically reversible, avoid cutting the computer’s original wiring, and expose test points for RGB, sync, ground and the converter’s supply rails.

A small breakout cable is preferable to soldering directly onto the computer. Use a shielded cable where possible, keep the RGB conductors similar in length, and provide a reliable 75-ohm termination at the receiver. The goal is to observe the original signal accurately before attempting to improve it.

Design The Analogue Front End

The analogue front end is where many otherwise impressive FPGA projects fail. A typical RGB computer output is designed for a terminated video load, so each colour input should present the correct impedance and avoid loading the X68000. A 75-ohm resistor to ground is common, though the exact arrangement depends on whether the source already includes a series resistor or expects a particular cable termination.

Feed each colour channel into a video-capable ADC or a carefully selected high-speed general-purpose converter. Eight bits per channel is workable for a retro display, while ten bits gives more headroom for clamping, filtering and later processing. The input range should accommodate black level and peak white without clipping. AC coupling can create a moving black level, so a clamp circuit or digitally managed baseline may be necessary if the source’s reference level is not stable.

Sync needs its own protection and conditioning. A resistor divider, comparator or sync separator can turn the original signal into clean logic levels, but the circuit must recognise whether the X68000 supplies separate horizontal and vertical sync or a composite arrangement. Add input protection, hysteresis and filtering carefully. Excessive filtering rounds the sync edge and can make a marginal mode harder to lock.

Use a short, controlled analogue path between connector, termination, filter and ADC. Keep the ADC reference and clock supplies quiet, separate high-current FPGA switching from the input stage, and join grounds deliberately rather than allowing return current to pass through the video connector shell. A metal enclosure connected to protective earth can reduce interference, but it must not create a dangerous path between equipment powered from different outlets.

Power deserves special attention in Australia. A converter intended for a 240 V environment should use a certified external USB-C or mains adaptor rather than an unapproved internal mains supply. A Jaycar-sourced project box and DC-DC module may be convenient for prototyping, but high-speed video hardware still needs proper insulation, fusing and strain relief before it is used beside a vintage computer.

Choose The FPGA Video Pipeline

The FPGA does not need to understand the X68000’s operating system or graphics hardware. It only needs to recover timing, sample the RGB data consistently, store enough lines or frames to cross between clock domains, and generate a standard HDMI-compatible output. A development board with an FPGA, external memory and an HDMI or DVI connector reduces the amount of high-speed PCB design required.

For an initial build, capture into a line buffer and produce a doubled or multiplied vertical output. This keeps latency low and can be sufficient when the input timing is regular. A frame buffer is more flexible: it can absorb unusual refresh rates, allow independent output timing and support menus or test patterns. The trade-off is added memory bandwidth, latency and firmware complexity.

Design approach	Strengths	Limitations	Suitable use
Analogue scaler IC	Fast development, established video processing, often includes sync handling	Less flexible with unusual X68000 modes, proprietary configuration, limited upgrade path	A practical appliance when supported input timings are known
FPGA line doubler	Low latency, transparent pixel processing, good learning platform	Needs reliable timing recovery and careful clock-domain design	15 kHz arcade-style modes and simple HDMI output
FPGA frame buffer	Handles mode changes, scaling and timing conversion well	Requires external RAM, more firmware and greater latency	A versatile converter for several X68000 display modes
FPGA with digital video input	Avoids analogue sampling errors when a digital source is available	Does not solve the original RGB interface problem	A later revision or experimental capture system
Dedicated retro scaler	Polished enclosure and broad compatibility	Higher cost, closed firmware and less control over X68000-specific behaviour	Users who want a ready-made solution rather than a build

A useful architecture has separate blocks for sync detection, sample-clock generation, pixel capture, buffering, scaling and HDMI transmission. Keep these blocks loosely coupled. The sync detector should report measured line and frame periods; the capture logic should decide whether the mode is valid; and the output block should continue generating a safe HDMI mode even while the input is disconnected.

The board’s HDMI output may actually be electrical DVI signalling over an HDMI connector. That is normally acceptable for video, but audio will require a separate design. If the FPGA board provides native TMDS outputs, follow its reference layout closely. If it uses a resistor network, keep the differential traces short and matched, and test with a known-good monitor before blaming the X68000.

Handle Scaling, Sync, And HDMI

A robust converter should measure timing instead of relying on a single hard-coded profile. Count FPGA clock cycles between horizontal sync edges, measure the active video interval, and record the number of lines per frame. The design can then classify a signal as a likely 15 kHz, 24 kHz or 31 kHz mode while still allowing unusual software-generated timings to pass through a configurable path.

Sampling phase affects picture quality. If the ADC clock is unrelated to the source pixel clock, the image can show shimmer, soft vertical edges or occasional colour instability. An FPGA can search for a stable sampling phase using transitions in the captured image, but a simpler design may use an oversampling clock and choose the best sample point during calibration. Preserve the original pixel geometry where practical; excessive smoothing makes Japanese text and fine game graphics look muddy.

The output timing should favour compatibility. A 720p60 HDMI signal is widely accepted by modern televisions, computer monitors and capture devices, while a 1080p output may introduce unnecessary scaling and processing delay. Centre the active image, offer integer scaling where it fits, and include adjustable borders so a slightly unusual source does not disappear off-screen. A nearest-neighbour option often looks best for pixel art, with a filtered mode available for users who prefer softer edges.

Sync loss handling is important during boot, mode changes and software that switches display settings. Blank the output or show a simple test pattern while the input is being reacquired rather than emitting random pixels. A small on-screen status display can report the detected line rate, frame rate, colour depth and scaling mode. Make it optional, since overlays can interfere with demonstrations and preservation captures.

HDMI hot-plug detection and EDID reading add another layer of reliability. The converter should wait for a monitor to identify its supported modes, then select a conservative timing. Some Australian-market televisions are surprisingly strict about older-looking video sources, especially inexpensive models sold through major retailers. Testing with a computer monitor, a lounge-room television and a capture card will reveal compatibility problems that a single display cannot.

Test, Enclose, And Document The Build

Testing should proceed from the cable inward. First verify continuity and pin assignment, then check the analogue waveform with the converter disconnected. Connect the front end without enabling the FPGA output, confirm that termination has not pulled the source level down, and compare the observed RGB signal against the direct output on a trusted display. Only then enable sampling and scaling.

Use software that exercises several video modes, including text-heavy screens, fast horizontal movement, dark scenes and transitions between resolutions. Look for colour-channel skew, clipped whites, crushed blacks, diagonal tearing and intermittent sync. A photographed test chart is useful, but real X68000 menus and games expose timing errors more clearly. Run the machine for an hour to find thermal drift in the ADC reference, FPGA regulator or enclosure.

The enclosure should provide strain relief for the computer cable, a secure HDMI socket and access to configuration controls without exposing the circuit board. Keep the converter away from the X68000’s ventilation openings and avoid placing a switching regulator directly beside the analogue input. A labelled mode indicator helps when several machines share a workbench, particularly during a busy retro meet in Melbourne, Sydney or Adelaide.

Document the pinout, measured waveforms, FPGA bitstream version and supported modes. The wider community is easier to reach through curated community resources, where owners often share service notes, software tools and compatibility discoveries. Record failures as carefully as successful settings; a future builder may be using a different X68000 revision, cable or display.

Sourcing parts locally can be a mixed experience. General electronics shops may carry connectors, resistors and enclosures, while specialist ADCs, FPGA boards and Japanese connectors often come from overseas distributors. Allow for GST, international postage and the occasional Australia Post delay when planning a repair or group build. Buying two critical ICs and sockets at the same time is often cheaper than stopping a project for a second shipment.

An FPGA RGB-to-HDMI converter becomes genuinely useful when it respects the original signal rather than hiding its quirks. Keep the analogue input reversible, make timing decisions visible, and design the firmware so unusual modes can be added later. Once the prototype displays stable text and fast graphics on several modern screens, publish the schematics, measurements and bitstream. That documentation gives other Australian owners a practical path from an aging RGB cable to a reliable digital display, while preserving the knowledge needed to keep the X68000 operating for many more years.